A liquid crystal panel (a liquid crystal display panel) has been in heavy usage in a display (a display module such as a liquid crystal display apparatus) such as a PC (personal computer) or a TV (television).
The following description deals with one example of driving circuits that drive a liquid crystal panel.
FIG. 13 is a block diagram showing a configuration of an X driver (a source driver) for supplying source lines with signals. The X-driver is one of the driving circuits. The technique relating to this kind of circuit is disclosed in Japanese examined patent publication No. 2747583 (publication date: Dec. 12, 1998), for example.
FIG. 14 is a time chart showing how main signals such as input signals, internal signals, and output signals behave during driving of the X-driver shown in FIG. 13.
As shown in FIG. 13, the X-driver includes a shift register 101, a latch A-circuit 102, a latch B-circuit 103, a decoder 104, a level shifter 105, and an analog switch group 106.
The shift register 101 receives a clock signal XCL and a start pulse (an input signal) XSP (see FIG. 14). The shift register 101 supplies internal output signals Q1 through QM to corresponding stages of the latch A-circuit 102, respectively. In FIG. 14, an internal output signal Qa indicates a signal which is outputted from the a-th stage of the shift register 101.
Symbols PD1 through PD4 indicate an input signal to be supplied to the first stage of the latch A-circuit 102. The input signal is a 4-bit digital signal.
The latch A-circuit 102 latches K-bit (here, K=4) signal PD1 through PD4 in parallel, and then outputs signals QA1 through QAM. Note that the signal QAa indicates a signal outputted from the a-th (1≦a≦M) stage of the latch A-circuit 102.
Namely, the latch A-circuit 102 sweeps the 4-bit data PD1 through PD4 in response to each rising edge of the output signals from the shift register 101 so as to output the signals QA1 through QAM.
The latch B-circuit 103 receives a latch clock input signal LCL. The latch B-circuit 103 sweeps the output signal QAa (1≦a≦M) of the latch A-circuit 102 in response to each falling edge of the latch clock input signal LCL so as to output a signal QB (4-bit signal DI1 through DI4).
The decoder 104 receives and decodes the 4-bit signal DI1 through DI4 so as to generate 16 data DO0 through DO15.
The level shifter 105 boosts the output signals of the decoder 104 up to a level of a liquid crystal driving voltage.
The analog switch group 106 supplies the output signals of the level shifter 105 to control terminals of respective analog switches so as to select one of 16(=24)-level gradation signals.
Note that each stage of the latch A-circuit 102 includes four (4) half-latch circuits 107, and that each stage of the latch B-circuit 103 includes four (4) half-latch circuits 108.
Each stage of the latch A-circuit 102 latches a 4-bit PD1 through PD4 in sync with an output Qn (n is an integer, and satisfies 1≦n≦M) from a corresponding stage of the shift register 101. All stages of the latch B-circuit 103 latch, in block, the signals QA1 through QAM in response to the latch clock input signal LCL. The decoder 104 decodes the 4-bit signal DI1 through DI4 for each stage.
One of the data DO0 through DO15 is selected in accordance with each result of the decoded 4-bit signal DI1 through DI4. This allows one of 16 analog switches in the analog switch group 106 to be selected via the level shifter 105.
This selection allows a target one of 16 gradation levels of the liquid crystal driving voltage that is externally supplied to be outputted to a source line as a final analog driver output O. Note that the symbol “i” indicates the data of i-row.
Pursuant to the demand that a large-sized screen be produced, conventional liquid crystal display apparatuses, having the above configuration, have been developed so as to be exploited in screens for TVs or PCs. Meanwhile, small and medium liquid crystal panel and liquid crystal driving circuit (liquid crystal driving apparatuses) suitable for a portable terminal such as a mobile phone have recently been developed such that the liquid crystal display apparatus is exploited in the portable terminal that has gained market share rapidly. With regard to the liquid crystal panel and liquid crystal driving circuit, strongly desired are downsizing, weight saving, low power consumption including battery-driving, multiple-output, speeding up, improvement in display quality, and low cost.
It is the tendency for the amount of data signal outputted at a same timing in block from a latch circuit to increase. The data signal is outputted from the latch circuit in sync with rising or falling edge of a latch signal LS. In the case of the configuration shown in FIG. 13, the data signal is outputted in sync with a falling edge of the latch clock input signal LCL. This tendency is derived from the affect by the large-sized liquid crystal panel and the multiple-output of the liquid crystal driving circuit.
On this occasion, as shown in FIG. 17, the power source current, which is supplied to the liquid crystal driving circuit, has a great peak value, thereby resulting in that the electric current consumption becomes great. FIG. 17 shows the measurement results of peak values of the power source current flowing in GND line (logical GND) in a logical circuit and a level shifter (a level shifter circuit), respectively.
Thus, according to the conventional technique, the current intensively flows in the logical GND, thereby giving rise to the occurrence of a great noise. This causes the problem that the data in a hold circuit section is changed.
In view of the circumstance, a liquid crystal display apparatus, which can reduce a peak value of the power source current in a driving circuit, has been developed. This kind of liquid crystal display apparatus is disclosed in Japanese unexamined patent publication No. 8-22267 published on Jan. 23, 1996, for example. FIG. 15 shows the configuration of such a conventional liquid crystal display apparatus.
A liquid crystal panel control apparatus 205 shown in FIG. 15 controls a liquid crystal panel 201. The liquid crystal panel control apparatus 205 receives a display data from a CPU 204, and generates clock pulses CL1 and CL2, a display data Din, and a frame signal FLM, respectively, which are required for the operation of the liquid crystal panel 201.
An alternating signal generation circuit 206 counts the clock pulse CL1 that corresponds to selection timing, and changes the polarity of an alternating signal M for every plurality of scanning lines during one frame (a display period during which one screen is displayed). This allows a frequency for the alternation to become high up to around hundreds of Hz, so as to avoid the flickering of the screen due to the alternation. Note that the flickering of the screen due to the alternation comes to an issue that the screen flickers, if the polarity of the alternating signal is changed for each frame, for example. This is because the frequency of the polarity inversion becomes relatively low.
A voltage generation circuit 207 generates driving voltages V1 through V6 that are supplied to a scanning driver 203 and a data driver 202. The voltage generation circuit 207 includes resistors that are connected in a series manner and operational amplifiers
The liquid crystal panel 201 includes m×n pixels. Namely, the liquid crystal display apparatus includes m scanning lines X1 through Xm and n signal lines Y1 through Yn.
The scanning driver 203 includes a shift register that carries out a shift operation in accordance with the clock pulse CL1. The scanning driver 203 allows a scanning line electrode to output the driving voltage generated by the voltage generation circuit 207 in accordance with an output signal of the shift register. The scanning driver 203 allows a corresponding scanning line electrode to have a selection level or a non-selection level.
More specifically, when the output signal of the shift register has a selection level, the scanning driver 203 outputs the driving voltage V1 to a corresponding scanning line electrode. Meanwhile, other scanning line driving voltages are the driving voltage V5 that corresponds to the non-selection level of the output signal of the shift register. The shift register sequentially shifts the selection level in sync with the clock pulse CL1. Because of this, a neighboring scanning line electrode has the selection level at the next timing. Thus, the scanning line electrodes are sequentially selected.
The scanning driver 203 switches the driving voltages V1 and V5 to the driving voltages V2 and V6, respectively, in accordance with the alternating signal M. More specifically, when the polarity of the alternating signal M is changed for every plurality of scanning lines during one frame, (i) the selection level is switched from the driving voltage V1 to V2 and vise versa, and (ii) the non-selection level is switched from the driving voltage V5 to V6 and vice versa.
The pixel data Din is serially supplied to a serial/parallel conversion circuit SPC in sync with the clock pulse CL2. A pixel signal corresponding to one scanning line is supplied to a signal line electrode in sync with a clock pulse CL2 during 1H period (within one cycle of the clock pulse CL1).
The pixel signal corresponding to one scanning line thus serially supplied is sent in parallel to a line data latch circuit C shown in FIG. 16. FIG. 16 shows how a driving circuit (the data driver 202), for use in a liquid crystal display apparatus shown in FIG. 15, is configured.
In the data driver 202, the image data is supplied to a level shifter circuit B from a line data latch circuit C that carries out the above described serial to parallel conversion. This allows the image data to be subject to a level shift processing. The line data latch circuit C is configured by a circuit to which a 5-volt power source is supplied. The line data latch circuit C outputs a signal having a high level of 5-volt or a signal having a low level of 0-volt.
In contrast, a driver A, for generating a display output signal that is supplied to a signal line, is configured by a switch MOSFET. The level shifter circuit B allows the output signal of the line data latch circuit C to be subject to the level shift processing. This is made for the purpose of outputting, without any level loss, a voltage, which falls within a relatively great range, such as the driving voltage V1, V3, V4, or V2 generated by the voltage generation circuit 207.
In the liquid crystal display apparatus, as shown in FIG. 16, a delay circuit D is provided between neighboring circuit groups CG. Accordingly, the display output signals outputted from the neighboring circuit groups CG have a phase lag, corresponding to the delay time of the delay circuit D, one another.
This allows the display output signals (display driving currents) to be dispersed and outputted for each circuit group CG. Because of this, the peak current is dispersed and flowed in the power source line, even if the number of the signal lines increases due to the large-sized screen or the high definition. Thus, it is possible to drastically reduce the peak current (the peak value of the power source current) flowing in the power source line (the logical GND line).
As described above, the liquid crystal panel includes many signal line electrodes (n signal line electrodes). The large-sized screen or the high definition causes the number n of the signal line electrodes to astronomically increase. Because of this, the liquid crystal panel includes a plurality of driving circuits having the configuration shown in FIG. 16. This gives rise to the configuration in which a plurality of semiconductor integration circuit apparatuses for driving the signal lines is mounted on a substrate (a mounting substrate).
Even in this case, it is possible in a driving circuit shown in FIG. 16 to disperse the driving current flowing in the power source line in each of the semiconductor integration circuit apparatuses, because the timing for the data latch signal has a phase lag one after another. Accordingly, it is also possible to reduce the peak value of the driving current even in the power source line on the mounting substrate.
Thus, according to the conventional driving circuit, the latch signal LS is delayed so as to reduce the peak value of the power source current.
However, this causes a setup time, provided between the latch signal LS and the start pulse signal in the next horizontal period, to be reduced as shown in FIG. 18.
This gives rise to the problem that the driving circuit erroneously operates for the reason that the latch signal LS cannot be appropriately recognized during one horizontal period.
This driving circuit is configured such that the latch signal LS simply has a phase lag by being sequentially subject to the delay circuits. Although the peak value of the power source current which is supplied to the data driver 202 (signal line driving circuit) can be reduced, the output signals of the data driver 202 also have a phase lag. In other words, the data driver 202 is not configured so as to output the analog signals at a time in block.
This results in that the charging time of the output signals is not uniform in the liquid crystal display apparatus, thereby causing nonuniform display to occur.